1. Field of the Invention
The present invention relates to a semiconductor memory device, and more specifically, to a semiconductor memory device adopting a redundancy system in which a defective memory cell is replaced by a spare memory cell.
2. Description of the Background Art
Conventionally, in a semiconductor memory device such as a dynamic random access memory (hereinafter referred to as a DRAM), a redundancy system is adopted in which a defective row or column is replaced by a spare row or column. A plurality of fuses for programming an address signal corresponding to a defective row or column are provided in a semiconductor memory device, and these fuses are blown on the wafer using a laser beam. When the address signal programmed by a plurality of fuses is input, a spare row or column is selected in place of the defective row or column. Thus, according to the redundancy system, a semiconductor memory device having a defective row or column can be repaired, and the yield of the semiconductor memory devices can be improved.
In some cases, however, a defective row or column is discovered after a semiconductor memory device is packaged, and in such cases, the semiconductor memory device cannot be repaired by the conventional redundancy system. Thus, in the recent years, a redundancy system is being developed which allows replacement of a defective row or column with a spare row or column even after the semiconductor memory device is packaged by the use of an electric fuse that is blown by a high voltage. In particular, in a system such as a server that requires high reliability to be maintained, a redundancy system that allows repair of a semiconductor memory device even after the semiconductor memory device is packaged is required as part of the improvement of system reliability.
Thus, the main object of the present invention is to provide a semiconductor memory device which allows easy determination as to whether a defective memory cell can be replaced by a spare memory cell even after packaging.
According to the present invention, a semiconductor memory device is provided with a plurality of memory cells to each of which is assigned in advance a unique address signal, a spare memory cell for replacing a defective memory cell, a decoder for selecting one of the plurality of memory cells according to an address signal externally supplied, a programming circuit having at least one first fuse for programming an address signal of the defective memory cell for rendering the decoder inactive and for selecting the spare memory cell in response to the fact that the address signal externally supplied is being programmed by at least one second fuse, a write/read circuit for performing a write/read operation of data signals of the selected memory cell and the spare memory cell, and a first determination circuit for determining whether an address signal is programmed in the programming circuit and outputting a signal of a level according to the result of determination. Thus, by detecting the level of an output signal from the first determination circuit, it can easily be determined whether the replacement of a defective memory cell with a spare memory cell is possible even after the semiconductor memory device has been packaged.
Preferably, multiple sets of a spare memory cell and a programming circuit are provided, and the first determination circuit determines whether there is a programming circuit in which an address signal is not being programmed, and outputs a signal of the level according to the result of determination. In this case, by detecting the level of the output signal from the first determination circuit, it becomes possible to determine whether there is a programming circuit in which an address signal is not programmed among the plurality of programming circuits, and it can be easily determined whether the replacement of a defective memory cell with a spare memory cell is possible.
Preferably, a second determination circuit is further provided for determining whether there is a programming circuit in which an address signal for a defective memory cell found after a semiconductor memory device is packaged is programmed and for outputting a signal of a level according to the result of determination. In this case, it becomes possible to prevent the same address signal from being programmed in two or more programming circuits so that the simultaneous selection of two or more spare memory cells can be prevented.
Preferably, the first determination circuit determines that there is no programming circuit in which an address signal is not programmed regardless of whether there is a programming circuit in which an address signal is not programmed when the second determination circuit determines that there is a programming circuit in which the address signal for the defective memory cell found after the semiconductor memory device is packaged is programmed. In this case, by simply detecting the level of an output signal from the first determination circuit, it can be determined whether there is a programming circuit in which an address signal is not programmed among the plurality of programming circuits, and the simultaneous selection of two or more spare memory cells can be prevented.
Preferably, a plurality of registers are further provided, each corresponding to one of the plurality of programming circuits and including a second fuse which is blown when an address signal is programmed in the corresponding programming circuit, and each for outputting a signal of a first level when the second fuse is blown and a signal of a second level when the second fuse is not blown. The first determination circuit makes the determination based on the output signals from the plurality of registers. In this case, it can be easily determined whether there is a programming circuit in which an address signal is not programmed among the plurality of programming circuits by detecting the level of the output signals from the plurality of registers.
Preferably, a data input/output terminal for communicating a data signal between the write/read circuit and outside and a switching circuit for supplying to the data input/output terminal a data signal read by the write/read circuit during a read mode and for supplying to the data input/output terminal an output signal from the first determination circuit during a determination mode are further provided. In this case, the output signal from the first determination circuit can be taken out to the outside via the data input/output terminal so that there is no need separately to provide a terminal for taking out the output signal from the first determination circuit to the outside.
Preferably, a blow circuit is further provided for selectively blowing at least one first fuse to program an address signal for a defective memory cell. In this case, the defective memory cell can be easily replaced with a spare memory cell even after the semiconductor memory device has been packaged.
Preferably, a blow voltage generating circuit is further provided for generating a blow voltage for blowing a first fuse and applying the generated blow voltage to the first fuse via the blow circuit. In this case, there is no need separately to apply a blow voltage for blowing a fuse to the semiconductor memory device.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.